Application Notes for R&S®FSPN

VCO MEASUREMENTS with R&S FSPN Phase Noise Analyzer

Next generation technologies in radar and satellite communication with high data rates call for innovative testing solutions to develop and manufacture RF components like voltage controlled oscillators (VCO). The R&S®FSPN phase noise analyzer increases efficiency and reproducibility of VCO characterization and phase noise measurements from lab to production.Voltage controlled oscillators are oscillators whose output frequency is controlled by means of an external tuning voltage, and they are used in a wide variety of electronic and RF applications like function generators, phase-locked loops including frequency synthesizers used in communication equipment. Different VCO design approaches yield different parameters and performance, and therefore it is important to measure or characterize VCOs under different conditions. This application note provides a short technical introduction to voltage controlled oscillators and explains the most common and the most important measurements made during the VCO characterization process.

17-May-2023 | AN-No. 1SL386

Verifying the clock source

The signal purity of clock sources has a direct impact on system performance. To ensure proper operation, it is necessary to verify that the purity meets the design requirements.

30-Sep-2021

Verifying additive phase noise and jitter attenuation of PLLs in high-speed digital designs

Increasing data rates in high-speed digital designs and wireless communications require SerDes PLLs and clock synthesizers with low additive phase noise and high jitter attenuation. Modern designs often follow a two-stage architecture, consisting of a jitter-attenuator and a frequency-synthesizer stage. Due to their high phase noise sensitivity, phase noise analyzers are the instruments of choice for these tests. To stimulate the PLL, an additional signal source with ultra low phase noise is required.

01-Aug-2018

Verifying the true jitter performance of clocks in high-speed digital designs

As the data rates in high-speed digital designs increase, the limits for overall system jitter become tighter. This especially applies to the various components of the clock tree, where the jitter limits for reference clocks, clock buffers and jitter attenuators are even tighter. Due to their high phase noise sensitivity, phase noise analyzers are the instruments of choice for these tests.

08-May-2018